FTQ=Val_0x0, TTC=Val_0x0, TSF=Val_0x0
Queue 0 Transmit Operation Mode Register
| FTQ | Flush Transmit Queue When this bit is set, the Tx Queue controller logic is reset to its default values. Therefore, all the data in the Tx Queue is lost or flushed. This bit is internally reset when the flushing operation is complete. Until this bit is reset, the user should not write to the ETH_MTL_TXQ0_OPERATION_MODE register. The data which is already accepted by the MAC transmitter is not flushed. It is scheduled for transmission and results in underflow and runt packet transmission. Note: The flush operation is complete only when the Tx Queue is empty and the application has accepted the pending Tx Status of all transmitted packets. Access restriction applies. Setting 1 sets. Self-cleared. Setting 0 has no effect. 0 (Val_0x0): Flush transmit queue is disabled 1 (Val_0x1): Flush transmit queue is enabled |
| TSF | Transmit Store and Forward When this bit is set, the transmission starts when a full packet resides in the MTL Tx Queue. When this bit is set, the TTC value is ignored. This bit should be changed only when the transmission is stopped. 0 (Val_0x0): Transmit store and forward is disabled 1 (Val_0x1): Transmit store and forward is enabled |
| TTC | Transmit Threshold Control These bits control the threshold level of the MTL Tx Queue. The transmission starts when the packet size within the MTL Tx Queue is larger than the threshold. In addition, full packets with length less than the threshold are also transmitted. These bits are used only when the TSF bit is reset. 0 (Val_0x0): 32 1 (Val_0x1): 64 2 (Val_0x2): 96 3 (Val_0x3): 128 4 (Val_0x4): 192 5 (Val_0x5): 256 6 (Val_0x6): 384 7 (Val_0x7): 512 |